CDC2536

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH 3-STATE OUTPUTS

SCAS377D – APRIL 1994 – REVISED OCTOBER 1998

4

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

CLKIN

3

I

Clock input. CLKIN provides the clock signal to be distributed by the CDC2536 clock-driver circuit. CLKIN

provides the reference signal to the integrated PLL that generates the clock output signals. CLKIN must have

a fixed frequency and fixed phase for the phase-lock loop to obtain phase lock. Once the circuit is powered up

and a valid CLKIN signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal

to its reference signal.

CLR

24

I

CLR is used for testing purposes only.

FBIN

26

I

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of the

six clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to obtain zero

phase delay between the FBIN and differential CLKIN inputs.

OE

5

I

Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE is

high, all outputs are in the high-impedance state. Since the feedback signal for the PLL is taken directly from

an output, placing the outputs in the high-impedance state interrupts the feedback loop; therefore, when a

high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is required before the PLL

obtains phase lock.

SEL

4

I

Output configuration select. SEL selects the output configuration for each output bank (e.g. 1

×, 1/2×, or 2×).

(see Tables 1 and 2).

TEST

25

I

TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST is low, all outputs operate

using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses the PLL

circuitry. TEST should be grounded for normal operation.

1Y1 – 1Y3

7, 10, 13

O

These outputs are configured by SEL to transmit one-half or one-fourth the frequency of the VCO. The

relationship between the CLKIN frequency and the output frequency is dependent on SEL. The duty cycle of

the Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal. Each output has an

internal series resistor to dampen transmission-line effects and improve the signal integrity at the load.

2Y1 – 2Y3

22, 19, 16

O

These outputs transmit one-half the frequency of the VCO. The relationship between the CLKIN frequency and

the output frequency is dependent on the frequency of the output being fed back to FBIN. The duty cycle of the

Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal. Each output has an

internal series resistor to dampen transmission-line effects and improve the signal integrity at the load.