CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER

WITH 3-STATE OUTPUTS

SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998

8

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

LOAD CIRCUIT FOR OUTPUTS

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

tphase error

1.5 V

1.5 V

3 V

0 V

1.5 V

VOH

VOL

Input

0.8 V

2 V

tr

tf

0.8 V

2 V

Output

From Output

Under Test

CL = 30 pF

(see Note A)

500

Ω

NOTES: A. CL includes probe and jig capacitance.

B. The outputs are measured one at a time with one transition per measurement.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 100 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

Figure 1. Load Circuit and Voltage Waveforms