CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER

WITH 3-STATE OUTPUTS

SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998

1

POST OFFICE BOX 655303

and Clock-Generation Applications

Outputs

Outputs to Operate at One-Half or Double

the Input Frequency

Synchronize the Outputs to the Clock Input

High-Speed Microprocessor

Transmission Lines

Significantly Reduces Power Dissipation

Switching Noise

PAH PACKAGE

(TOP VIEW)

15 16

4Y3

GND

4Y2

GND

4Y1

GND

GND

3Y3

GND

39

38

37

36

35

34

33

32

31

30

29

28

27

17

1

2

3

4

5

6

7

8

9

10

11

12

13

GND

1Y1

GND

1Y2

GND

1Y3

GND

GND

2Y1

18 19 20 21

51 50 49 48 47

52

46

44 43 42

45

22 23 24 25 26

41 40

14

NC – No internal connection

description

The CDC586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely

align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically

designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz

a properly terminated 50-

W transmission line.

Copyright

© 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-

ΙΙB is a trademark of Texas Instruments Incorporated.