PCI2031 datasheet(51/70 Pages) TI

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PCI2031

PCI-TO-PCI BRIDGE

SCPS017A – DECEMBER 1997 – REVISED JANUARY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

diagnostic status register

Bit

Name

Diagnostic status

Type

R/W

Default

Diagnostic status

Type:

Read only, read/write (see individual bit descriptions)

Offset:

72h–73h

Default:

0000h

Description: The diagnostic status register is used to reflect the bridge diagnostic status.

Table 21. Diagnostic Status Register

BIT

TYPE

FUNCTION

15–12

Reserved

R/W

Bridge detected a parity error while mastering on the secondary bus. When set, bit 11 indicates that the secondary bus

master detected a parity error. Writing a 1 to this bit clears it.

0 = No parity error detected

1 = Parity error detected

R/W

Bridge detected a parity error while mastering on the primary bus. When set, bit 10 indicates that the primary bus master

detected a parity error. Writing a 1 to this bit clears it.

0 = No parity error detected

1 = Parity error detected

R/W

Secondary-slave discard timer expired. Writing a 1 to this bit clears it.

0 = Discard timer not expired

1 = Discard timer expired

R/W

Primary-slave discard timer expired. Writing a 1 to this bit clears it.

0 = Discard timer not expired

1 = Discard timer expired

7–5

Reserved

R/W

Serial EEPROM detect status. When bit 4 is cleared, it indicates that the serial EEPROM block detected an EEPROM.

Writing a 1 to this bit clears it. This bit is encoded as:

0 = Serial EEPROM block detected an EEPROM.

1 = Serial EEPROM block did not detect an EEPROM.

R/W

Serial EEPROM block error status. Bit 3 indicates the error status of the serial EEPROM block. This bit is set when a data

error has occurred in the serial EEPROM block. Writing a 1 to this bit clears it. This bit is encoded as:

0 = No error detected.

1 = Data error detected.

External arbiter enable pin status. Bit 2 contains the current state of the external pin external arbiter enable.

0 = Signal low

1 = Signal high

Serial EEPROM block status. Bit 1 indicates the status of the serial EEPROM block. When set, bit 1 indicates that the

serial EEPROM block is busy.

0 = Serial EEPROM block not busy

1 = Serial EEPROM block busy

R/W

Arbiter timeout status. Bit 0 indicates the status of the arbiter timer. When set, bit 0 indicates that a bus master did not

begin the cycle within 16 clocks. Writing a 1 to this bit clears it. This bit is encoded as:

0 = No timeout (default).

1 = Master requesting the bus did not start cycle within 16 clocks.

PCI2031 Datasheet(PDF) 51 Page - Texas Instruments

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