TDA8025 datasheet(13/38 Pages) PHILIPS

13 / 38 page

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

13 of 38

NXP Semiconductors

TDA8025

IC card interface

8.4 Input and output circuits

When pins I/O and I/OUC are driven HIGH using an 11 k

Ω resistor between pins I/O and

VCC and/or between pins I/OUC and VDD(INTF), both lines enter the idle state. Pin I/O is

referenced to VCC and pin I/OUC to VDD(INTF), thus allowing operation at VCC ≠ VDD(INTF).

The ﬁrst side on which a falling edge occurs becomes the master. An anti-latch circuit

disables falling edge detection on the other line, making it the slave. After a time delay

td(edge), the NMOS transistor on the slave-side is turned on. It then sends logic 0 to the

master-side. When the master returns logic 1, the PMOS transistor on the slave side is

turned on during the time delay (tpu). After this sequence, both the master and slave return

to their idle states.

The active pull-up feature ensures fast LOW-to-HIGH transitions making the TDA8025

capable of delivering more than 1 mA, up to an output voltage of 0.9 VCC, at a load of

80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the

internal pull-up resistor value and load current. The current sent to and received from the

card’s I/O lines is internally limited to 15 mA at a maximum frequency of 1 MHz.

8.5 Inactive mode

After a power-on reset, the circuit enters the inactive mode, ensuring only the minimum

number of circuits are active while the TDA8025 waits for the microcontroller to start a

session. The inactive mode conditions are as follows:

• all card contacts are inactive. The impedance between the contacts and GND is

approximately 200

Ω.

• pins I/OUC, AUX1UC and AUX2UC are high-impedance using the 11 k

Ω pull-up

resistor connected to VDD(INTF)

• the voltage generators and crystal oscillator are stopped

• the voltage supervisor is active

• the internal oscillator runs in low frequency mode

Fig 7.

Output voltage and current on pins I/O, AUX1 and AUX2 as a function of time

during LOW-to-HIGH transitions

t (ns)

100

001aai964

IOH I/O

(A)

V I/O

(V)

IOH I/O

V I/O

TDA8025 Datasheet(PDF) 13 Page - NXP Semiconductors

TDA8025 Datasheet(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL