SN54HC161 datasheet(12/24 Pages) TI

12 / 24 page

SN54HC161, SN74HC161

4BIT SYNCHRONOUS BINARY COUNTERS

SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

The glitch on RCO is caused because the propagation delay of the rising edge of QA of the second stage is

shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, QA, QB, QC, and QD

(ENT

× QA × QB × QC × QD). The resulting glitch is about 7−12 ns in duration. Figure 3 shows the condition in

which the glitch occurs. For simplicity, only two stages are being considered, but the results can be applied to

other stages. QB, QC, and QD of the first and second stage are at logic one, and QA of both stages are at logic

zero (1110 1110) after the first clock pulse. On the rising edge of the second clock pulse, QA and RCO of the

first stage go high. On the rising edge of the third clock pulse, QA and RCO of the first stage return to a low level,

and QA of the second stage goes to a high level. At this time, the glitch on RCO of the second stage appears

because of the race condition inside the chip.

CLK

ENT1

QB1, QC1, QD1

QA1

RCO1, ENT2

QB2, QC2, QD2

QA2

RCO2

Glitch (7−12 ns)

Figure 3

The glitch causes a problem in the next stage (stage three) if the glitch is still present when the next rising clock

edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than the

inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (tg). In other words,

fmax = 1/(tpd CLK-to-RCO + tg). For example, at 25°C at 4.5-V VCC, the clock-to-RCO propagation delay is

43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the

cascaded counters can use is 18 MHz. The following tables contain the fclock, tw, and fmax specifications for

applications that use more than two ’HC161 devices cascaded together.

SN54HC161 Datasheet(PDF) 12 Page - Texas Instruments