SN54HC161, SN74HC161

4BIT SYNCHRONOUS BINARY COUNTERS

SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003

2

POST OFFICE BOX 655303

description/ordering information (continued)

These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As

presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs

to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function for the ’HC161 devices is asynchronous. A low level at the clear (CLR) input sets all four of

the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without

additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).

Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a

can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the

level of CLK.

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that

modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of

the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the

stable setup and hold times.