SN54HC166, SN74HC166

8-BIT PARALLEL-LOAD SHIFT REGISTERS

SCLS117B – DECEMBER 1982 – REVISED MAY 1997

6

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

TA = 25°C

SN54HC166

SN74HC166

UNIT

VCC

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

0

6

0

4.2

0

5

fclock

Clock frequency

4.5 V

0

31

0

21

0

25

MHz

6 V

0

36

0

25

0

29

2 V

100

150

125

CLR low

4.5 V

20

30

25

t

Pulse duration

6 V

17

26

21

ns

tw

Pulse duration

2 V

80

120

100

ns

CLK high or low

4.5 V

16

24

20

6 V

14

20

17

↑

2 V

145

220

180

SH/LD high before CLK

↑

4.5 V

29

44

36

6 V

25

38

31

↑

2 V

80

120

100

SER before CLK

↑

4.5 V

16

24

20

6 V

14

20

17

↑

2 V

100

150

125

tsu

Setup time

CLK INH low before CLK

↑

4.5 V

20

30

25

ns

6 V

17

26

21

↑

2 V

80

120

100

Data before CLK

↑

4.5 V

16

24

20

6 V

14

20

17

↑

2 V

40

60

50

CLR inactive before CLK

↑

4.5 V

8

12

10

6 V

7

10

9

↑

2 V

0

0

0

SH/LD high after CLK

↑

4.5 V

0

0

0

6 V

0

0

0

↑

2 V

5

5

5

SER after CLK

↑

4.5 V

5

5

5

th

Hold time

6 V

5

5

5

ns

th

Hold time

↑

2 V

0

0

0

ns

CLK INH high after CLK

↑

4.5 V

0

0

0

6 V

0

0

0

↑

2 V

5

5

5

Data after CLK

↑

4.5 V

5

5

5

6 V

5

5

5