SN54HC166, SN74HC166

8-BIT PARALLEL-LOAD SHIFT REGISTERS

SCLS117B – DECEMBER 1982 – REVISED MAY 1997

3

POST OFFICE BOX 655303

logic diagram (positive logic)

1D

C1

15

9

7

6

13

SH/LD

CLR

CLK

CLK INH

QH

234

5

10

11

12

14

SER

AB

CD

E

F

G

H

R

1D

C1

R

1D

C1

R

1D

C1

R

1D

C1

R

1D

C1

R

1D

C1

R

1D

C1

R

1

Pin numbers shown are for the D, J, N, and W packages.

typical clear, shift, load, inhibit, and shift sequence

Clear

Load

Inhibit

H

H

H

H

H

H

H

HHH

L

L

L

L

L

L

CLK

CLK INH

SER

A

B

C

D

E

F

G

H

SH/LD

CLR

QH

Parallel

Inputs

Serial Shift

Serial Shift