SN54HC646, SN74HC646

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCLS150B – DECEMBER 1982 – REVISED MAY 1997

3

POST OFFICE BOX 655303

FUNCTION TABLE

INPUTS

DATA I/O

OPERATION OR FUNCTION

OE

DIR

CLKAB

CLKBA

SAB

SBA

A1– A8

B1– B8

OPERATION OR FUNCTION

X

X

↑

X

X

X

Input

Unspecified†

Store A, B unspecified†

X

XX

↑

X

X

Unspecified†

Input

Store B, A unspecified†

H

X

↑

↑

X

X

Input

Input

Store A and B data

H

X

H or L

H or L

X

X

Input disabled

Input disabled

Isolation, hold storage

L

L

X

X

X

L

Output

Input

Real-time B data to A bus

L

L

X

H or L

X

H

Output

Input

Stored B data to A bus

L

H

X

X

L

X

Input

Output

Real-time A data to B bus

L

H

H or L

X

H

X

Input

Output

Stored A data to B bus

† The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at

the bus terminals is stored on every low-to-high transition of the clock inputs.

‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DW, JT, NT, and W packages.

A1

4

B1

20

4D

5

7

7

5

1

1

6D

≥1

≥1

1

2

A2

5

B2

19

A3

6

B3

18

A4

7

B4

17

A5

8

B5

16

A6

9

B6

15

A7

10

B7

14

A8

11

B8

13

OE

G3

21

3 EN2 [AB]

G5

22

SBA

3 EN1 [BA]

3

DIR

23

CLKBA

1

CLKAB

G7

2

SAB

C6

C4