SMSNE555 datasheet(5/5 Pages) SECOS

5 / 5 page

01-Jun-2006 Rev. A

Page 5of 5

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Elektronische Bauelemente

Single Timer

Application Circuit

Application Notes

The application circuit shows astable mode configuration.

Pin 6 (Threshold) is tied to Pin 2 (Trigger) and Pin 4 (Reset) is tied to VCC (Pin 8). The external capacitor C1

of Pin 6 and Pin 2 charges through RA, RB and discharge through RB only. In the internal circuit of

GSCNE555, one input of the upper comparator is at voltage of 2/3VCC (R1=R2=R3), another input is

connected to Pin 6. As soon as C1 is charging to higher than 2/3VCC, transistor Q1 is turned ON and

discharge C1 to collector voltage of transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One

input of lower comparator is at voltage of 1/3VCC, discharge transistor Q1 turn off and C1 charges through RA

and RB. Therefore, flip-flop circuit is set output high.

That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB, output is

low. The charge time (output is high) t1 is 0.693 (RA+RB) C1 and the discharge time (output is low) T2 is

0.693RB*C1.

Vcc

Vcc 2

=0.693

T1=0.693*(RA+RB)*C1

Thus the total period time T is given by

T2=0.693*RB*C1

T=T1+T2=0.693(RA+2RB)*C1

Then the frequency of astable mode is given by

f =

The duty cycle is given by

D.C. =

FLIP-FLOP

SPNE555

Vcc

(RA+2RB)*C1

1.44

RA+2RB

Vcc

SMSNE555

SMSNE555 Datasheet(PDF) 5 Page - SeCoS Halbleitertechnologie GmbH