ADP3121

http://onsemi.com

5

Characteristic

Unit

Max

Typ

Min

Symbol

Test Conditions

LOW−SIDE DRIVER

Timeout Delay

SW = 5 V

SW = PGND

90

70

170

110

ns

Over−voltage Protection Threshold

1.5

3.5

V

UNDERVOLTAGE LOCKOUT

UVLO Voltage

1.5

3.0

V

Hysteresis

250

mV

5. ALL limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods

APPLICATIONS INFORMATION

Theory of Operation

The ADP3121 is optimized for driving two N−channel

MOSFETs in a synchronous buck converter topology. A

single PWM input signal is all that is required to properly

drive the high side and the low−side MOSFETs. Each driver

is capable of driving a 3 nF load at speeds up to 500 kHz. A

functional block diagram of ADP3121 is shown in Figure 1.

Low−Side Driver

The low−side driver is designed to drive a ground

referenced N−channel MOSFET. The bias to the low−side

When the driver is enabled, the driver output is 180

° out

of phase with the PWM input. When the ADP3121 is

disabled, the low−side gate is held low.

High−Side Driver

The high−side driver is designed to drive a floating

N−channel MOSFET. The bias voltage for the high−side

driver is developed by an external bootstrap supply circuit

that is connected between the BST and SW pins.

The bootstrap circuit comprises Diode D1 and Bootstrap

high−side gate drive voltage and to limit the switch node

slew rate (called a Boot−Snap

t circuit). When the

ADP3121 starts up, the SW pin is at ground, so the bootstrap

input goes high, the high−side driver begins to turn on the

enough gate−to−source voltage is provided. To complete the

cycle, Q1 is switched off by pulling the gate down to the

voltage at the SW pin. When the low−side MOSFET, Q2,

turns on, the SW pin is pulled to ground. This allows the

The output of the high−side driver is in phase with the

PWM input. When the driver is disabled, the high−side gate

is held low.

Overlap Protection Circuit

The overlap protection circuit prevents both of the main

power switches, Q1 and Q2, from being on at the same time.

This is done to prevent shoot−through currents from flowing

through both power switches and the associated losses that

can occur during their on/off transitions. The overlap

protection circuit accomplishes this by adaptively

controlling the delay from the Q1 turn−off to the Q2 turn−on,

and by internally setting the delay from the Q2 turn−off to

the Q1 turn−on.

To prevent the overlap of the gate drives during the Q1

turn−off and the Q2 turn−on, the overlap circuit monitors the

voltage at the SW pin. When the PWM input signal goes low,

Q1 begins to turn off (after propagation delay). Before Q2

can turn on, the overlap protection circuit makes sure that

SW has first gone high and then waits for the voltage at the

pin falls to 1 V, Q2 begins turn−on. If the SW pin has not

gone high first, the Q2 turn−on is delayed by a fixed 150 ns.

By waiting for the voltage on the SW pin to reach 1 V or for

the fixed delay time, the overlap protection circuit ensures

that Q1 is off before Q2 turns on, regardless of variations in

temperature, supply voltage, input pulse width, gate charge,

and drive current. If SW does not go below 1 V after 190 ns,

DRVL turns on. This can occur if the current flowing in the

output inductor is negative and flows through the high−side

MOSFET body diode.

OVERVOLTAGE PROTECTION

The ADP3121 includes an over−voltage protection

(OVP) feature to protect the CPU from high voltages even

before the main controller has enough VCC to operate. The

ADP3121 looks at the SW node during startup. If the voltage

on SW is greater than the OVP threshold, DRVL is latched

on and DRVH latched off. An OVP on the SW node will

cause DRVL to go high and remain high.

To prevent false triggering of OVP, an input logic

detection latch is set on the first occurrence of either IN or