EPA018B

ISSUED 11/01/2007

High Efficiency Heterojunction Power FET

Specifications are subject to change without notice.

Excelics Semiconductor, Inc. 310 De Guigne Drive, Sunnyvale, CA 94085

page 1 of 3

Revised November 2007

Chip Thickness: 75 ± 13 micron

All Dimensions in Microns

FEATURES

•

VERY HIGH fmax: 120GHz

•

+20.0dBm TYPICAL OUTPUT POWER

•

13.0dB TYPICAL POWER GAIN AT 18 GHz

•

TYPICAL 0.75dB NOISE FIGURE AND 12.5dB

ASSOCIATED GAIN AT 12GHz

•

0.3 X 180 MICRON RECESSED “MUSHROOM” GATE

•

•

ADVANCED EPITAXIAL HETEROJUNCTION

PROFILE PROVIDES EXTRA HIGH POWER

EFFICIENCY, AND HIGH RELIABILITY

•

Idss SORTED IN 5 mA PER BIN RANGE

Caution! ESD sensitive device.

SYMBOL

PARAMETERS/TEST CONDITIONS

1

MIN

TYP

MAX

UNITS

Output Power at 1dB Compression

f = 12GHz

f = 18GHz

18.0

20.0*

20.0*

dBm

Gain at 1dB Compression

f =12GHz

f = 18GHz

13.0

14.5

13.0

dB

PAE

Power Added Efficiency at 1dB Compression Vds=6V, Ids=50% Idss

f=12Ghz

48

%

NF

Noise Figure, f = 12GHz

0.75

dB

Ga

Associated Gain, f = 12GHz

12.5

dB

Saturated Drain Current

30

55

80

mA

Transconductance

35

60

mS

Pinch-off Voltage

-1.0

-2.5

V

Drain Breakdown Voltage

-9

-15

V

Source Breakdown Voltage

-7

-14

V

Thermal Resistance (Au-Sn Eutectic Attach)

185

*P1dB = 21.5dBm can be obtained with 8v/50% Idss bias. Consult factory for wafer selection.

MAXIMUM RATINGS AT 25°C

SYMBOL

CHARACTERISTIC

ABSOLUTE

1

CONTINUOUS

2

Vds

Drain to Source Voltage

12V

6 V

Gate to Source Voltage

-8V

- 3 V

Ids

Drain Current

Idss

Idss

Forward Gate Current

9mA

1.5 mA

Input Power

16dBm

@ 3dB compression

Channel Temperature

175°C

150°C

Storage Temperature

-65/175°C

-65/150°C

Total Power Dissipation

740mW

625mW

Note: 1. Exceeding any of the above ratings may result in permanent damage.

2. Exceeding any of the above ratings may reduce MTTF below design goals.