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AI325 Datasheet(PDF) 2 Page - A1 PROs co., Ltd. |
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AI325 Datasheet(HTML) 2 Page - A1 PROs co., Ltd. |
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2 / 8 page ![]() 2 Ai325 Block Diagram Pin Description Description Vertical register transfer clock 4 Vertical register transfer clock 3 Vertical register transfer clock 2 Vertical register transfer clock 1 Ground Output amplifier gate bias Output amplifier source bias CCD Output signal Ground Substrate(Overflow drain)bias Protection bias Reset gate clock No connection Horizontal register transfer clock 1 Horizontal register transfer clock 2 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol V¥ õ4 V¥ õ3 V¥ õ2 V¥ õ1 GND VGG VSS VOUT GND VSUB VP V RG NC VDD H¥ õ1 H¥ õ2 Output amplifier drain bias Description No. Symbol Absolute Maximum Ratings VP V RG NC VGG VSS VOUT VDD GND VSUB HCCD GND 8 7 V¥ õ1 H¥ õ1 H¥ õ2 6 5 4 3 2 1 9 10 11 12 13 14 15 16 V¥ õ2 V¥ õ3 V¥ õ4 PD -10 to +20 -0.3 to +27 -55 to +10 V¥ õ1, 2, 3, 4 - GND V¥ õ1, 2, 3, 4 - VP V¥ õ1, 2, 3, 4 - VSUB Vertical clock input voltage -0.3 to +55 -0.3 to +18 -55 to +10 VSUB - GND VDD, VOUT, VSS - GND VDD, VOUT, VSS - VSUB Value Unit Symbol Parameter Substrate voltage Supply voltage V V V V V V -17 to +17 Between horizontal clock and vertical clock input pins H¥ õ1 , H¥ õ2 - V¥ õ4 V Output pin voltage ¥ Õ RG, VGG - GND ¥ Õ RG, VGG - VSUB -10 to +15 -55 to +10 V V Protective circuit voltage Vp - VSUB -65 to 0.3 V Horizontal clock input voltage H¥ õ1 , H¥ õ2 - GND -10 to +15 V Between vertical clock input pins V¥ õx - V¥ õy -10 to +15 V Storage temperature TSTG -30 to 80 ¡ É Operation temperature TOPR -10 to 60 ¡ É |
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