SN74ACT8994

DIGITAL BUS MONITOR

IEEE STD 1149.1 (JTAG) SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER

SCAS196E – JULY 1990 – REVISED DECEMBER 1996

5

POST OFFICE BOX 655303

detailed description (continued)

The test-cell register (TCR) is a data register that performs PSA operations on the data bus or on the contents

of RAM. During PSA operations, the TCR is a linear-feedback shift register. The CTLR configures the data

masking and controls the feedback for PSA operations. The boundary-scan register (BSR), header register

(HR), and bypass register (BR) are data registers that can be serially accessed through the TAP interface.

instruction register

The 8-bit instruction register (IR) contains the DBM current instruction, which controls all operations of the

device. When the IR is placed in the scan path, the IR status word is loaded into the IR and shifted out on TDO

when the new instruction is shifted in.

The IR status word contains four status bits. The IRERR status bit is asserted when an opcode that does not

exhibit even parity is loaded into the IR. The OVF status bit is asserted when the RAM address counter is

incremented past its maximum value of 3FFh (register value given in hexadecimal format, indicated by the letter

h following the value). The RUN and EOT status bits pertain to on-line testing and are asserted when a protocol

is active (RUN) or the end of the protocol is reached (EOT).

boundary-scan register

The boundary-scan register (BSR) is a 24-bit register that includes one boundary-scan cell (BSC) for each of

the non-JTAG input and output pins of the device, two BSCs for PIO (one for input data and one for output data),

and one BSC for the PIO direction signal. The BSR is used to capture the data appearing at the device periphery

and to apply test data to the device outputs.

bypass register

The bypass register (BR) is a 1-bit register required by IEEE Standard 1149.1-1990. It provides an abbreviated

scan path through the DBM when the current test operations do not require it to access one of the other data

registers.

control register

The 45-bit control register (CTLR) issues configuration, control, and enable signals to the device. Data shifted

into the CTLR configures the data mask and feedback for PSA operations. It also configures the programmable

clock interface and selects the test operations to be performed (see test operations).

event-qualification register 1

Event-qualification register 1 (EQR1) is a 32-bit register that configures the DBM for on-line testing

(event-qualified testing). Data shifted into EQR1 selects and controls one of eight event-qualification protocols

and configures the event and status signals. The event signal triggers test operations according to the protocol

being executed. The status signal is output via EQO. EQR1 also contains the loop counter, which controls the

number of times an event-qualification protocol is executed.

event-qualification register 2

Event-qualification register 2 (EQR2) is used to load the event counter, expected data, and mask data

(16-word-deep register files) for event-qualified tests. Depending on the current instruction, it is either 48 or 56

bits in length and can be thought of as three 16-bit data segments and two 4-bit address segments. One 4-bit

address segment addresses the event counter, while the other 4-bit address segment addresses the expected

data and mask data.

The register files can be accessed using IEEE-Standard-1149.1-1990-compatible instructions or DMA

instructions. When using IEEE-Standard-1149.1-1990-compatible instructions, EQR2 is configured as a 56-bit

register. The data appearing in the 16-bit data segments is loaded into or out of the addresses specified by the

register’s two 4-bit address segments.