SN74ACT8994

DIGITAL BUS MONITOR

IEEE STD 1149.1 (JTAG) SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER

SCAS196E – JULY 1990 – REVISED DECEMBER 1996

2

POST OFFICE BOX 655303

description (continued)

The DBM receives instructions via the IEEE Standard 1149.1-1990 test access port (TAP) interface. The TAP

interface consists of test clock (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO)

pins.

The DBM can be operated in the off-line mode or the on-line mode. In the off-line mode, the device performs

test operations independent of system conditions. Off-line test operations include parallel-signature analysis

(PSA) on the contents of RAM and external test.

In the on-line mode, the DBM can be configured to perform test operations that are initiated based on system

conditions and that operate synchronously to a logical combination of one or more system clocks. The device

allows sample, storage, and/or PSA operations to be performed according to one of eight protocols. Compare

patterns, which can be stored in the event-qualification module (EQM), allow the user to define specific values

of the 16-bit bus for which the test operations are to be performed.

The 1024-word by 16-bit RAM and the EQM register files can be serially accessed using

IEEE-Standard-1149.1-1990-compatible read and write instructions. However, direct memory access (DMA)

instructions also are provided to speed transfer of large amounts of data to and from the RAM and EQM.

The polynomial input/output (PIO) is a bidirectional pin used to cascade more than one DBM to provide

signature analysis on a bus larger than 16 bits.

The SN74ACT8994 is characterized for operation from 0

°C to 70°C.