LTC2224 datasheet(14/24 Pages) LINER

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LTC2224

2224fa

During the sample phase when ENC is low, the transistors

connect the analog inputs to the sampling capacitors and

they charge to, and track the differential input voltage.

When ENC transitions from low to high, the sampled input

voltage is held on the sampling capacitors. During the hold

phase when ENC is high, the sampling capacitors are

disconnected from the input and the held voltage is passed

to the ADC core for processing. As ENC transitions from

high to low, the inputs are reconnected to the sampling

capacitors to acquire a new sample. Since the sampling

capacitors still hold the previous sample, a charging glitch

proportional to the change in voltage between samples will

be seen at this time. If the change between the last sample

and the new sample is small, the charging glitch seen at

the input will be small. If the input change is large, such as

the change seen with input frequencies near Nyquist, then

a larger charging glitch will be seen.

Single-Ended Input

For cost sensitive applications, the analog inputs can be

driven single-ended. With a single-ended input the har-

monic distortion and INL will degrade, but the SNR and

DNL will remain unchanged. For a single-ended input, AIN+

should be driven with the input signal and AIN– should be

connected to 1.6V or VCM.

Common Mode Bias

For optimal performance the analog inputs should be

driven differentially. Each input should swing

±0.5V for

the 2V range or

±0.25V for the 1V range, around a

common mode voltage of 1.6V. The VCM output pin (Pin

44) may be used to provide the common mode bias level.

VCM can be tied directly to the center tap of a transformer

to set the DC input level or as a reference level to an op amp

differential driver circuit. The VCM pin must be bypassed to

ground close to the ADC with a 2.2

µF or greater capacitor.

Input Drive Impedance

As with all high performance, high speed ADCs, the

dynamic performance of the LTC2224 can be influenced

by the input drive circuitry, particularly the second and

third harmonics. Source impedance and input reactance

can influence SFDR. At the falling edge of ENC, the sample-

and-hold circuit will connect the 1.6pF sampling capacitor

to the input pin and start the sampling period. The sam-

pling period ends when ENC rises, holding the sampled

input on the sampling capacitor. Ideally the input circuitry

should

fast

enough

fully

charge

the sampling capacitor during the sampling period

1/(2FENCODE); however, this is not always possible and the

incomplete settling may degrade the SFDR. The sampling

glitch has been designed to be as linear as possible to

minimize the effects of incomplete settling.

For the best performance, it is recommended to have a

source impedance of 100

Ω or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2224 being driven by an RF

transformer with a center tapped secondary. The second-

ary center tap is DC biased with VCM, setting the ADC input

Ω

0.1

µF

AIN

–

12pF

2.2

µF

VCM

LTC2224

ANALOG

INPUT

0.1

µFT1

1:1

T1 = MA/COM ETC1-1T

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

2224 F03

Figure 3. Single-Ended to Differential Conversion

Using a Transformer

APPLICATIO S I FOR ATIO

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