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LTC2224

2224fa

APPLICATIO S I FOR ATIO

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits and the overflow bit.

Digital Output Buffers

Figure 13 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, which

are isolated from the ADC power and ground. The addi-

tional N-channel transistor in the output driver allows

operation down to voltages as low as 0.5V. The internal

resistor in series with the output makes the output appear

as 50

Ω to external circuitry and may eliminate the need for

external damping resistors.

2224 F12a

ENC–

1.6V

VTHRESHOLD = 1.6V

ENC+

0.1

µF

LTC2224

2224 F12b

ENC–

ENC+

130

Ω

3.3V

130

Ω

MC100LVELT22

LTC2224

Ω

Figure 12a. Single-Ended ENC Drive,

Not Recommended for Low Jitter

Figure 12b. ENC Drive Using a CMOS to PECL Translator

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTC2224 should drive a minimal

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. For full speed

operation the capacitive load should be kept under 5pF.

Lower OVDD voltages will also help reduce interference

from the digital outputs and improve the SNR.

Data Format

The LTC2224 parallel digital output can be selected for

offset binary or 2’s complement format. The format is

selected with the MODE pin. Connecting MODE to GND or

1/3VDD selects offset binary output format. Connecting

MODE to 2/3VDD or VDD selects 2’s complement output

format. An external resistor divider can be used to set the

1/3VDD or 2/3VDD logic values. Table 2 shows the logic

states for the MODE pin.

LTC2224

2224 F13

OVDD

VDD

0.1

µF

Ω

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

Figure 13. Digital Output Buffer

Table 1. Output Codes vs Input Voltage

AIN

+ – AIN–

D11 – D0

(2V Range)

(Offset Binary)

(2’s Complement)

>+1.000000V

1111 1111 1111

0111 1111 1111

+0.999512V

1111 1111 1111

0111 1111 1111

+0.999024V

1111 1111 1110

0111 1111 1110

+0.000488V

1000 0000 0001

0000 0000 0001

0.000000V

1000 0000 0000

0000 0000 0000

–0.000488V

0111 1111 1111

1111 1111 1111

–0.000976V

0111 1111 1110

1111 1111 1110

–0.999512V

0000 0000 0001

1000 0000 0001

–1.000000V

0000 0000 0000

1000 0000 0000

<–1.000000V

0000 0000 0000

1000 0000 0000

Table 2. MODE Pin Function

Clock Duty

MODE Pin

Output Format

Cycle Stablizer

Offset Binary

Off

1/3VDD

Offset Binary

2/3VDD

2’s Complement

VDD

2’s Complement

Off

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