REV. E

–12–

AD7846

AD7846*

+5V

DATA BUS

*LINEAR CIRCUITRY

OMITTED FOR CLARITY

CS

LDAC

CLR

R/

W

DB0–DB15

MC68000

DS

DTACK

R/

W

A1–A23

ADDRESS

DECODE

ADDRESS BUS

D0–D15

Figure 25. AD7846-to-MC68000 Interface

DIGITAL FEEDTHROUGH

In the preceding interface configurations, most digital inputs to

the AD7846 are directly connected to the microprocessor bus.

Even when the device is not selected, these inputs will be con-

stantly changing. The high frequency logic activity on the bus

can feed through the DAC package capacitance to show up as

noise on the analog output. To minimize this Digital Feed-

through isolate the DAC from the noise source. Figure 26 shows

an interface circuit which isolates the DAC from the bus.

AD7846*

+5V

DATA BUS

*LINEAR CIRCUITRY

OMITTED FOR CLARITY

CS

LDAC

CLR

DB0–DB15

MICRO-

PROCESSOR

A1–A15

ADDRESS

DECODE

ADDRESS BUS

D0–D15

R/

W

R/

W

2

74LS245

B BUS

A BUS

DIR

G

Figure 26. AD7846 Interface Circuit Using Latches to Mini-

mize Digital Feedthrough

Note that to make use of the AD7846 readback feature using

the isolation technique of Figure 26, the latch needs to be

bidirectional.

APPLICATION HINTS

Noise

In high resolution systems, noise is often the limiting factor.

With a 10 volt span, a 16-bit LSB is 152

µV (–96 dB). Thus, the

noise floor must stay below –96 dB in the frequency range of

interest. Figure 7 shows the noise spectral density for the AD7846.

Grounding

As well as noise, the other prime consideration in high resolu-

tion DAC systems is grounding. With an LSB size of 152

µV

and a load current of 5 mA, 1 LSB of error can be introduced

by series resistance of only 0.03

Ω.

Figure 27 below shows recommended grounding for the AD7846

in a typical application.

ANALOG SUPPLY

DIGITAL SUPPLY

+15V

0V

–15V

+5V DGND

SIGNAL

GROUND

AD7846*

AD588*

R1

R4

(+5V TO –5V)

R2

R3

R5

*ADDITIONAL PINS

OMITTED FOR CLARITY

Figure 27. AD7846 Grounding

R1 to R5 represent lead and track resistances on the printed

circuit board. R1 is the resistance between the Analog Power

Supply ground and the Signal Ground. Since current flowing in

R1 is very low (bias current of AD588 sense amplifier), the

effect of R1 is negligible. R2 and R3 represent track resistance

between the AD588 outputs and the AD7846 reference inputs.

Because of the Force and Sense outputs on the AD588, these

resistances will also have a negligible effect on accuracy.

R4 is the resistance between the DAC output and the load. If

can be trimmed out in the calibration cycle. R5 is the resistance

between the load and the analog common. If the output voltage

is sensed across the load, R5 will introduce a further gain error

which can be trimmed out. If, on the other hand, the output

voltage is sensed at the analog supply common, R5 appears as

part of the load and therefore introduces no errors.

Printed Circuit Board Layout

Figure 28 shows the AD7846 in a typical application with the

AD588 reference, producing an output analog voltage in the

±10 volts range. Full scale and bipolar zero adjustment are

provided by potentiometers R2 and R3. Latches (2

× 74LS245)

isolate the DAC digital inputs from the active microprocessor

bus and minimize digital feedthrough.

The printed circuit board layout for Figure 28 is shown in Fig-

ures 29 and 30. Figure 29 is the component side layout while

Figure 30 is the solder side layout. The component overlay is

shown in Figure 31.

In the layout, the general grounding guidelines given in Figure

27 are followed. The AD588 and AD7846 are as close as pos-

sible, and the decoupling capacitors for these are also kept as

close to the device pins as possible.