LTC2225 datasheet(13/20 Pages) LINER

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LTC2225

2225fa

APPLICATIO S I FOR ATIO

An optional clock duty cycle stabilizer circuit can be used

if the input clock has a non 50% duty cycle. This circuit

uses the rising edge of the CLK pin to sample the analog

input. The falling edge of CLK is ignored and the internal

falling edge is generated by a phase-locked loop. The input

clock duty cycle can vary and the clock duty cycle stabilizer

will maintain a constant 50% internal duty cycle. If the

clock is turned off for a long period of time, the duty cycle

stabilizer circuit will require a hundred clock cycles for the

PLL to lock onto the input clock. To use the clock duty

cycle stabilizer, the MODE pin should be connected to

1/3VDD or 2/3VDD using external resistors.

The lower limit of the LTC2225 sample rate is determined

by droop of the sample-and-hold circuits. The pipelined

architecture of this ADC relies on storing analog signals on

small valued capacitors. Junction leakage will discharge

the capacitors. The specified minimum operating fre-

quency for the LTC2225 is 1Msps.

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits, and the overflow bit.

It is not recommended to drive the SENSE pin with a logic

device. The SENSE pin should be tied to the appropriate

level as close to the converter as possible. If the SENSE pin

is driven externally, it should be bypassed to ground as

close to the device as possible with a 1

µF ceramic capacitor.

Input Range

The input range can be set based on the application. The

2V input range will provide the best signal-to-noise perfor-

mance while maintaining excellent SFDR. The 1V input

range will have better SFDR performance, but the SNR will

degrade by 3.8dB.

Driving the Clock Input

The CLK input can be driven directly with a CMOS or TTL

level signal. A differential clock can also be used along with

a low-jitter CMOS converter before the CLK pin (see

Figure 8).

The noise performance of the LTC2225 can depend on the

clock signal quality as much as on the analog input. Any

noise present on the clock signal will result in additional

aperture jitter that will be RMS summed with the inherent

ADC aperture jitter.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2225 is 10Msps.

For the ADC to operate properly, the CLK signal should

have a 50% (

±10%) duty cycle. Each half cycle must have

at least 40ns for the ADC internal circuitry to have enough

settling time for proper operation.

Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter

CLK

100

Ω

0.1

µF

4.7

µF

FERRITE

BEAD

CLEAN

SUPPLY

IF LVDS USE FIN1002 OR FIN1018.

FOR PECL, USE AZ1000ELT21 OR SIMILAR

2225 F08

LTC2225

Table 1. Output Codes vs Input Voltage

AIN

+ – AIN–

D11 – D0

(2V Range)

(Offset Binary)

(2’s Complement)

>+1.000000V

1111 1111 1111

0111 1111 1111

+0.999512V

1111 1111 1111

0111 1111 1111

+0.999024V

1111 1111 1110

0111 1111 1110

+0.000488V

1000 0000 0001

0000 0000 0001

0.000000V

1000 0000 0000

0000 0000 0000

–0.000488V

0111 1111 1111

1111 1111 1111

–0.000976V

0111 1111 1110

1111 1111 1110

–0.999512V

0000 0000 0001

1000 0000 0001

–1.000000V

0000 0000 0000

1000 0000 0000

<–1.000000V

0000 0000 0000

1000 0000 0000

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