TCM38C17IDL

QCombo

™ FOUR-CHANNEL (QUAD) PCM COMBO

SLWS040C – JUNE 1996 – REVISED OCTOBER 1999

3

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AREF

2

Analog reference point (mid-supply). This voltage is generated internally at a nominal 2.375 V. An

external decoupling capacitor (0.1

µF) should be connected from AREF to AVSS for filtering purposes.

0ANLGIN+

6

I

Noninverting analog input to uncommitted transmit operational amplifier for channel 0

0ANLGIN –

5

I

Inverting analog input to uncommitted transmit operational amplifier for channel 0

1ANLGIN+

12

I

Noninverting analog input to uncommitted transmit operational amplifier for channel 1

1ANLGIN –

11

I

Inverting analog input to uncommitted transmit operational amplifier for channel 1

2ANLGIN+

43

I

Noninverting analog input to uncommitted transmit operational amplifier for channel 2

2ANLGIN –

44

I

Inverting analog input to uncommitted transmit operational amplifier for channel 2

3ANLGIN+

37

I

Noninverting analog input to uncommitted transmit operational amplifier for channel 3

3ANLGIN –

38

I

Inverting analog input to uncommitted transmit operational amplifier for channel 3

ASEL

24

I

A-law and

µ-law operation select. When ASEL is connected to ground, A-law is selected. When ASEL is

connected to VDD,

µ-law is selected (digital).

AVDD

46

Analog supply voltage, 5 V,

±5%

AVSS

3

Analog ground return for AVDD supply

DVDD

20

Digital supply voltage, 5 V,

±5%

DVDDPLL

21

Phase-locked loop supply voltage, 5 V,

±5%

DVSSPLL

23

Phase-locked loop ground return for DVDDPLL supply

DVSS

19

Digital ground return for DVDD supply

0FS

31

I

Frame synchronization clock input/time slot enable for channel 0 TX and RX (digital)

1FS

30

I

Frame synchronization clock input/time slot enable for channel 1 TX and RX (digital)

2FS

29

I

Frame synchronization clock input/time slot enable for channel 2 TX and RX (digital)

3FS

28

I

Frame synchronization clock input/time slot enable for channel 3 TX and RX (digital)

0GSR

8

I

Receive amplifier gain-set input (channel 0). The ratio of an external voltage divider network connected to

0PWRO – and 0PWRO+ determines the receive amplifier gain. Maximum gain occurs when 0GSR is

connected to 0PWRO –, and minimum gain occurs when it is connected to 0PWRO+ (analog).

1GSR

14

I

Receive amplifier gain-set input (channel 1). The ratio of an external voltage divider network connected to

1PWRO – and 1PWRO+ determines the receive amplifier gain. Maximum gain occurs when 1GSR is

connected to 1PWRO –, and minimum gain occurs when it is connected to 1PWRO+ (analog).

2GSR

41

I

Receive amplifier gain-set input (channel 2). The ratio of an external voltage divider network connected to

2PWRO – and 2PWRO+ determines the receive amplifier gain. Maximum gain occurs when 2GSR is

connected to 2PWRO –, and minimum gain occurs when it is connected to 2PWRO+ (analog).

3GSR

35

I

Receive amplifier gain-set input (channel 3). The ratio of an external voltage divider network connected to

3PWRO – and 3PWRO+ determines the receive amplifier gain. Maximum gain occurs when 3GSR is

connected to 3PWRO –, and minimum gain occurs when it is connected to 3PWRO+ (analog).

0GSX

4

O

Output terminal of internal uncommitted transmit operational amplifier for channel 0 (analog)

1GSX

10

O

Output terminal of internal uncommitted transmit operational amplifier for channel 1 (analog)

2GSX

45

O

Output terminal of internal uncommitted transmit operational amplifier for channel 2 (analog)

3GSX

39

O

Output terminal of internal uncommitted transmit operational amplifier for channel 3 (analog)

MCLK

22

I

Master clock input (2.048 MHz) (digital)

PCMIN

25

I

Transmit PCM input (digital)

PCMOUT

27

O

Transmit PCM output (digital)

0PDN

16

I

Power-down select for channel 0. This channel of the device is inactive with a CMOS low-level input to

0PDN and active with a CMOS high-level input to the terminal (digital).

1PDN

17

I

Power-down select for channel 1. This channel of the device is inactive with a CMOS low-level input to

1PDN and active with a CMOS high-level input to the terminal (digital).

2PDN

32

I

Power-down select for channel 2. This channel of the device is inactive with a CMOS low-level input to

2PDN and active with a CMOS high-level input to the terminal (digital).