THS1031SOIC datasheet(6/26 Pages) TI

6 / 26 page

THS1031

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics, AVDD = 3 V, DVDD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2 V

input span from 0.5 V to 2.5 V, external reference, PGA = 1X, TA = –40°C to 85°C (unless otherwise

noted) (continued)

dynamic performance (ADC and PGA)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f = 3.5 MHz

8.2

ENOB

Effective number of bits

f = 3.5 MHz, AVDD = 5 V

8.8

Bits

ENOB

Effective number of bits

f = 15 MHz

7.7

Bits

f = 15 MHz, AVDD = 5 V

7.64

f = 3.5 MHz

SFDR

Spurious free dynamic range

f = 3.5 MHz, AVDD = 5 V

SFDR

Spurious free dynamic range

f = 15 MHz

f = 15 MHz, AVDD = 5 V

52.4

f = 3.5 MHz

– 58.2

– 54.7

THD

Total harmonic distortion

f = 3.5 MHz, AVDD = 5 V

– 68.7

THD

Total harmonic distortion

f = 15 MHz

–47

f = 15 MHz, AVDD = 5 V

– 51.9

f = 3.5 MHz

51.2

SNR

Signal to noise

f = 3.5 MHz, AVDD = 5 V

SNR

Signal-to-noise

f = 15 MHz

f = 15 MHz, AVDD = 5 V

49.3

f = 3.5 MHz

51.1

SINAD

Signal to noise and distortion

f = 3.5 MHz, AVDD = 5 V

SINAD

Signal-to-noise and distortion

f = 15 MHz

48.1

f = 15 MHz, AVDD = 5 V

47.7

PGA

PARAMETER

MIN

TYP

MAX

UNIT

Gain range (linear scale)

0.5

V/V

Gain step size (linear scale)

0.5

Gain error from nominal

Number of control bits

Bits

clamp DAC

PARAMETER

MIN

TYP

MAX

UNIT

Resolution

Bits

DAC output range

REFBF

REFTF

Clamping analog output voltage range

0.1

AVDD– 0.1

Clamping analog output voltage error

– 40

+ 40

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