THS1050

10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS278 – APRIL 2000

2

POST OFFICE BOX 655303

functional block diagram

Digital Error Correction

S/H

Stage 1

Stage 10

Reference

3.0 V

2.0 V

AVDD/2

Timing

VIN–

VREFOUT+

VCM

CLK+

DVSS

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

AVDD DVDD

D/A

Σ

A/D

Σ

D/A

A/D

A/D

VREFOUT–

VREFIN+

VREFIN–

CLK–

1

1

1

Buffer

DRVDD

AVSS

DRVSS

Stages 2 – 9

VIN+

900

Ω

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AVDD

2, 5, 12 43,

45, 47

I

Analog power supply

AVSS

1, 11, 13, 41,

42, 44, 46

I

Analog ground return for internal analog circuitry

CLK+

15

I

Clock input

CLK–

16

I

Complementary clock input

D9–D0

25–34

O

Digital data output bits; LSB= D0, MSB = D9 (2s complement output format)

DRVDD

24, 37, 38

I

Digital output driver supply

DRVSS

23, 39, 40

I

Digital output driver ground return

DVDD

17, 20, 22

I

Positive digital supply

DVSS

18, 19, 21

I

Digital ground return

VBG

10

O

Band gap reference. Bypass to ground with a 1

µF and a 0.01 µF chip capacitor.

VCM

48

O

Common mode voltage output. Bypass to ground with a 0.1

µF and a 0.01 µF chip device capacitor.

VIN+

3

I

Analog signal input

VIN–

4

I

Complementary analog signal input

VREFIN –

7

I

External reference input low

VREFIN+

8

I

External reference input high

VREFOUT+

9

O

Internal reference output. Compensate with a 1

µF and a 0.01 µF chip capacitor.

VREFOUT –

6

O

Internal reference output. Compensate with a 1

µF and a 0.01 µF chip capacitor.