THS5641A

8-BIT, 100 MSPS, CommsDAC

™

DIGITAL-TO-ANALOG CONVERTER

SLAS277 –MARCH 2000

17

POST OFFICE BOX 655303

APPLICATION INFORMATION

analog current outputs

Figure 26 shows a simplified schematic of the current source array output with corresponding switches.

Differential PMOS switches direct the current of each individual PMOS current source to either the positive

output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined

by the stack of the current sources and differential switches, and is typically >300 k

Ω in parallel with an output

capacitance of 5 pF.

Output nodes IOUT1 and IOUT2 have a negative compliance voltage of –1 V, determined by the CMOS process.

Beyond this value, transistor breakdown may occur, resulting in reduced reliability of the THS5641A device. The

compliance is limited to 0.6 V. Exceeding the positive compliance voltage adversely affects distortion

performance and integral nonlinearity. The optimum distortion performance for a single-ended or differential

output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed 0.5 V (e.g. when

applying a 50

Ω doubly terminated load for 20 mA full-scale output current). Applications requiring the

AVDD

Current Source Array

IOUT1

IOUT2

RLOAD

RLOAD

Current

Sources

Switches

Figure 26. Equivalent Analog Current Output

Figure 27(a) shows the typical differential output configuration with two matched externally resistor loads. The

nominal resistor load of 50

current. The output impedance of the THS5641A depends slightly on the output voltage at nodes IOUT1 and

IOUT2. Consequently, for optimum dc integral nonlinearity, the configuration of Figure 27(b) should be chosen.

In this I–V configuration, terminal IOUT1 is kept at virtual ground by the inverting operational amplifier. The

complementary output should be connected to ground to provide a dc current path for the current sources

switched to IOUT2. Note that the INL/DNL specifications for the THS5641A are measured with IOUT1

maintained at virtual ground. The amplifier’s maximum output swing and the DAC’s full-scale output current

output, thereby reducing the operational amplifier slew-rate requirements. In this configuration, the op amp

should operate on a dual supply voltage due to its positive and negative output swing. Node IOUT1 should be

selected if a single-ended unipolar output is desirable.