THS4061, THS4062

180-MHz HIGH-SPEED AMPLIFIERS

SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000

16

POST OFFICE BOX 655303

APPLICATION INFORMATION

driving a capacitive load

Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are

taken. The first is to realize that the THS406x has been internally compensated to maximize its bandwidth and

slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the

output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for

capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of

the amplifier, as shown in Figure 25. A minimum value of 20

Ω should work well for most applications. For

example, in 75-

Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance

loading and provides the proper line impedance matching at the source end.

+

_

THS406x

CLOAD

510

Ω

Input

Output

510

Ω

20

Ω

Figure 25. Driving a Capacitive Load

circuit layout considerations

In order to achieve the levels of high frequency performance of the THS406x, it is essential that proper

printed-circuit board high frequency design techniques be followed. A general set of guidelines is given below.

In addition, a THS406x evaluation board is available to use as a guide for layout or for evaluating the device

performance.

components with a low inductive ground connection. However, in the areas of the amplifier inputs and

output, the ground plane can be removed to minimize the stray capacitance.

capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers

depending on the application, but a 0.1-

µF ceramic capacitor should always be used on the supply terminal

of every amplifier. In addition, the 0.1-

µF capacitor should be placed as close as possible to the supply

terminal. As this distances increases, the inductance in the connecting trace makes the capacitor less

effective. The designer should strive for distances of less than 0.1 inches between the device power

terminals and the ceramic capacitors.

inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly

to the printed-circuit board is the best implementation.

series inductance has been minimized. To realize this, the circuit layout should be made as compact as

possible thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting

input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray

capacitance at the input of the amplifier.