THS8134, THS8134A, THS8134B

TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER

WITH TRI-LEVEL SYNC GENERATION

SLVS205D – MAY 1999 – REVISED MARCH 2000

13

POST OFFICE BOX 655303

analog (DAC) outputs

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DAC resolution

8

8

bits

INL

Integral nonlinearity

Static, best fit

±0.2

±1.2

LSB

DNL

Differential nonlinearity

Static

±0.2

±1

LSB

PSRR

Power supply ripple rejection ratio of DAC

f = 100 kHz (see Note 4)

37

dB

PSRR

yj

output (full scale)

f = 1 MHz (see Note 4)

43

dB

XTALK

Crosstalk between channels

f up to 30 MHz, (see Note 5)

–55

dB

VO(ref)

Voltage reference output

1.30

1.35

1.40

V

ro(VREF)

VREF output resistance

7K

11K

15K

W

G(DAC)

DAC gain factor

See

Table 4

Imbalance between DACs, (KIMBAL)

See Note 6

±5%

Imbalance between positive and negative sync,

(KIMBAL(SYNC))

See Note 6

±2%

VO(

C)

DAC output compliance voltage (sync+video)

RL = 37.5 Ω, See Note 7

1

1.2

V

VO(DAC)

DAC output compliance voltage (sync+video)

RL = 75 Ω, See Note 7

2

2.4

V

Internal reference

AGY

24

26.67

28

GBR sync-on-green and YPbPr sync-on-Y/sync-

Internal reference

ABPb and ARPr

17.3

18.67

19.7

mA

yg

y

y

on-all

External reference

AGY

24.9

26.67

27.2

mA

I(S)

External reference

ABPb and ARPr

17.5

18.67

19.3

I(FS)

Internal reference

AGY

24

26.67

28

GBR sync on all

Internal reference

ABPb and ARPr

24

26.67

28

mA

GBR sync-on-all

External reference

AGY

24.9

26.67

27.2

mA

External reference

ABPb and ARPr

24.9

26.67

27.2

ro

DAC output resistance

See Note 10

57

92

k

Ω

CO

DAC output capacitance (pin capacitance)

8

pF

tr(DAC)

DAC output current rise time

10% to 90% of full scale

2

ns

tf(DAC)

DAC output current fall time

10% to 90% of full scale

2

ns

td(A)

Analog output delay

Measured from CLK=VIH(min) to 50% of full-scale

transition, See Note 8

9

ns

tS

Analog output settling time

Measured from 50% of full scale transition on output

to output settling, within 2%, See Note 9

5

9

ns

SNR

Signal -to-noise ratio

1 MHz, –1 dBFS digital sine input, measured from

0 MHz to 8.8 MHz

53

dB

SFDR

Spurious-free dynamic range

1 MHz, –1 dBFS digital sine input, measured from

0 MHz to 8.8 MHz

62

dB

BW(1 dB)

Bandwidth

See Note 11

40

MHz

NOTES:

4. PSRR is measured with a 0.1

µF capacitor between the COMP and AVDD terminal; with a 0.1 µF capacitor connected between the VREF terminal and

AVSS. The ripple amplitude is within the range 100 mVp-p to 500 mVp-p with the DAC output set to full scale and a double-terminated 75

Ω (=37.5 Ω)

load. PSRR is defined as 20

× log(ripple voltage at DAC output/ripple voltage at AVDD input). Limits from characterization only.

5.

Crosstalk spec applies to each possible pair of the 3 DAC outputs. Limits from characterization only.

6.

The imbalance between DACs applies to all possible pairs of the three DACs. KIMBAL is assured over full temperature range. In parts labeled

THS8134CPHP, KIMBAL(SYNC) is assured at 25°C. In parts labeled THS8134ACPHP, KIMBAL(SYNC) is assured over the full temperature range.

7.

Nominal values at R(FS) = R(FSnom) : Maximum values at R(FS) = R(FSnom) ÷ 1.2. Maximum limits from characterization only.

8.

This value excludes the digital process delay, td(D). Limit from characterization only.

9.

Maximum limit from characterization only

10.

Limit from characterization only

11.

This bandwidth relates to the output amplitude variation in excess of the droop from the sinx/x sampled system. Since the output is a sample-and-hold

signal, a sin(

π × Fin ÷ Fclk) ÷ (π × Fin ÷ Fclk) roll-off is observed, which accounts e.g. at Fin = 40 MHz and Fclk = 80 MSPS for –3.92 dB signal drop (sync

droop). The total DAC output variation (device droop) consists of this and an additional amount (excess droop) caused by the output impedance of the

device, as shown in Table 5.