TL16PC564B, TL16PC564BLV

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998

6

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

INTER-

FACE†

I/O

DESCRIPTION

RST

11

M

O

This is the qualified active-low reset signal. RST has a fail-safe open-drain output.

RTS

35

U

O

Request to send is an active-low signal. When active, RTS informs the modem of the data set

that the UART is ready to receive data. RTS is set to its active state by setting the RTS modem

control register bit and is set to its inactive (high) state either as a result of a reset, doing

loop-mode operation, or by resetting bit 1 (RTS) of the MCR.

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

53

55

56

57

58

59

61

65

S

I

When SSAB is high, this is the subsystem address bus and SAD (7– 0) is the subsystem data

bus. When SSAB is low, this bus is not used and SAD(7– 0) is the subsystem multiplexed

address/data bus.

SA8

24

S

I

Address bit 8 is bit 8 of the subsystem address bus.

SAD0

SAD1

SAD2

SAD3

SAD4

SAD5

SAD6

SAD7

25

23

20

19

18

17

15

14

S

I/O

Subsystem address/data 7 – 0. This is a multiplexed bidirectional address/data bus to the

attribute-memory DPRAM and CCRs when SSAB is low. This becomes a bidirectional data bus

when SSAB is high.

SELZ / I

28

S

I

Select Zilog or Intel mode. SELZ / I is used to select between a Zilog-like or Intel-like

microcontroller. 1 = Zilog, 0 = Intel.

SIN

33

U

I

Serial data input. SIN moves information from the communication line or modem to the

TL16PC564B UART receiver circuits. Data on the serial bus is disabled when operating in the

loop mode.

SOUT

45

U

O

Serial out. SOUT is the composite serial data output to a connected communication device.

SOUT is set to the marking (logic 1) state as a result of a reset.

SSAB

3

S

I

Separate subsystem address bus. SSAB is used to select between a multiplexed address/data

bus subsystem interface (SSAB = 0) and a subsystem interface with separate address and data

buses (SSAB = 1). This signal has an internal pulldown resistor.

STSCHG

74

H

O

Status change. STSCHG is an optional active-low output signal used to alert the host that a

subsystem write to attribute memory has occurred. This signal has an open-drain output.

TESTOUT

70

M

O

This is a production test output.

UARTCLK

51

M

O

UART clock. UARTCLK is a clock output whose frequency is determined by the frequency on

XIN and the divisor value on the PGMCLK register.

VCC

10,21, 22, 36,

47,52, 60,

72, 86, 97

M

3.3-V or 5-V supply voltage

VTEST

2

M

I

VTEST is an active-high production test input with an internal pulldown resistor. It can be left

open or tied to ground.

WE

89

H

I

Write enable. WE is an active-low input signal used for strobing attribute-memory write data into

the card. This signal has an internal pullup resistor

WR(R/W)

31

S

I

Write or read/write enable. WR(R/W) is the active-low write enable in the Intel mode and

read/write in the Zilog mode.

XIN

42

M

I

Crystal input. XIN is a clock input divided internally based on the PGMCLK register value, then

used as the primary UART clock input.

† Host = H, Subsystem = S, UART = U, Miscellaneous = M