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TL16PC564B Datasheet(PDF) 7 Page - Texas Instruments

Part # TL16PC564B
Description  PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
PDF  33 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TL16PC564B Datasheet(HTML) 7 Page - Texas Instruments

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TL16PC564B, TL16PC564BLV
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998
7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
detailed description
reset-validation circuit
A reset-validation circuit has been implemented to qualify the active-high RESET input. At power up, the level
on the RST output is unknown. Whenever RESET is stable for at least eight ARBCLKIs, RST reflects the
inverted state of that stable value of RESET. Any changes on RESET must be valid for eight ARBCLKI clocks
before the change is reflected on RST. This 8-clock filter provides needed hysteresis on the master reset input.
RST is driven by a low-noise, open-drain, fail-safe output buffer.
host CPU memory map
The host CPU attribute memory space is mapped as follows:
Host CPU Address Bits 9–1 (HA0 = 0)
Attribute Memory Space
0 – 255
CIS
256
CCR0
257
CCR1
258
CCR2
259
CCR3
260
CCR4
261
CCR5
262
CCR6
263
CCR7
The host CPU I/O space is mapped as follows:
Address Mode (hex)
Normal Mode
COM1
COM2
COM3
COM4
I/O Space
0 (DLAB = 0)†
3F8
2F8
3E8
2E8
UART receiver buffer register (RBR) – read only
0 (DLAB = 0)†
3F8
2F8
3E8
2E8
UART transmitter holding register (THR) – write only
0 (DLAB = 1)†
3F8
2F8
3E8
2E8
UART divisor latch LSB (DLL)
1 (DLAB = 0)†
3F9
2F9
3E9
2E9
UART interrupt enable register (IER)
1 (DLAB = 1)†
3F9
2F9
3E9
2E9
UART divisor latch MSB (DLM)
2
3FA
2FA
3EA
2EA
UART interrupt identification register (IIR) – read only
2
3FA
2FA
3EA
2EA
UART FIFO control register (FCR) – write only
3
3FB
2FB
3EB
2EB
UART line control register (LCR)
4
3FC
2FC
3EC
2EC
UART modem control register (MCR) – bit 5 read only
5
3FD
2FD
3ED
2ED
UART line status register (LSR)
6
3FE
2FE
3EE
2EE
UART modem status rgister (MSR)
7
3FF
2FF
3EF
2EF
UART scratch register (SCR)
† DLAB is bit 7 of the line control register (LCR).
subsystem memory map
The subsystem attribute memory space is mapped as follows:
Subsystem Address Bits 8 – 0
Attribute Memory Space
0 – 255
CIS
256
CCR0
257
CCR1
258
CCR2
259
CCR3
260
CCR4
261
CCR5
262
CCR6
263
CCR7



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