TLC2932

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997

15

POST OFFICE BOX 655303

APPLICATION INFORMATION

gain of VCO and PFD

Figure 24 is a block diagram of the PLL. The

countdown N value depends on the input

frequency and the desired VCO output frequency

according to the system application requirements.

operating characteristics of the device as shown

Figures 8, 9, 10, and 11 as shown in Figure 24(c).

The parameters for the block diagram with the

units are as follows:

external counter

When a large N counter is required by the

application, there is a possibility that the PLL

response becomes slow due to the counter

response delay time. In the case of a high

frequency application, the counter delay time

should be accounted for in the overall PLL design.

for optimum temperature performance, a resistor value of 3.3 k

Ω with a 3-V supply and a resistor value of 2.5

k

Ω for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choice

but a carbon-compositiion resistor can be used with excellent results also. A 0.22

µF capacitor should be

connected from the BIAS terminal to ground as close to the device terminals as possible.

hold-in range

From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter

configurations shown in Figure 25 is as follows:

Dw

H ]

0.8 Kp

K

V

K

f

(

R)

Where

Divider

(KN = 1/N)

PFD

(Kp)

VCO

(KV)

LPF

(Kf)

TLC2932

f REF

VOH

fMAX

fMIN

VIN MIN

VIN MAX

–2

π

2

π

–

π

0

π

Range of

Comparison

VOH

VOL

Kp =

VOH – VOL

4

π

KV =

2

π(fMAX – fMIN)

VIN MAX – VIN MIN

Figure 24. Example of a PLL Block Diagram

(a)

(c)

(b)