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TLC2932IPWLE Datasheet(PDF) 17 Page - Texas Instruments |
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TLC2932IPWLE Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 24 page ![]() TLC2932 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION basic design example (continued) Assume the loop has to have a 100 µs settling time (ts) with a countdown N = 8. Using the Type 1, second order response curves of Figure 26, a value of 4.5 radians is selected for ωnts with a damping factor of 0.7. This selection gives a good combination for settling time, accuracy, and loop gain margin. The initial parameters are summarized in Table 5. The loop constants, KV and Kp, are calculated from the data sheet specifications and Table 6 shows these values. The natural loop frequency is calculated as follows: wnts + 4.5 Then wn + 4.5 100 ms + 45 k-radians sec Since Table 5. Design Parameters PARAMETER SYMBOL VALUE UNITS Division factor N 8 Lockup time t 100 µs Radian value to selected lockup time ωnt 4.5 rad Damping factor ζ 0.7 Table 6. Device Specifications PARAMETER SYMBOL VALUE UNITS VCO gain 76.6 Mrad/V/s fMAX 70 MHz fMIN KV 20 MHz VIN MAX 5 V VIN MIN 0.9 V PFD gain Kp 0.342357 V/rad Table 7. Calculated Values PARAMETER SYMBOL VALUE UNITS Natural angular frequency ωn 45000 rad/sec K = (KV • Kp)/N 3.277 Mrad/sec Lag-lead filter Calculated value Nearest standard value R1 15870 16000 Ω Calculated value Nearest standard value R2 308 300 Ω Selected value C1 0.1 µF |
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