TLC2932IPWR datasheet(22/24 Pages) TI

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TLC2932

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

1/2 fosc

Phase

Comparator

AGND

DGND

REF IN

DVDD

AVDD

VDD

LOGIC VDD (Digital)

LOGIC GND (Digital)

SELECT

FIN – A

VCO INHIBIT

PFD INHIBIT

VCO GND

VCO IN

BIAS

VCO VDD

VCO

R1†

Divide

0.22

µF

FIN – B

† RBIAS resistor

VCO OUT

PFD OUT

Figure 28. Evaluation and Operation Schematic

PCB layout considerations

The TLC2932 contains a high frequency analog oscillator; therefore, very careful breadboarding and

printed-circuit-board (PCB) layout is required for evaluation.

The following design recommendations benefit the TLC2932 user:

D External analog and digital circuitry should be physically separated and shielded as much as possible to

reduce system noise.

D RF breadboarding or RF PCB techniques should be used throughout the evaluation and production

process.

D Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance

and resistance. The ground plane is the better choice for noise reduction.

D LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply point

available in the system to minimize supply cross-coupling.

D VCO VDD to GND and LOGIC VDD to GND should be decoupled with a 0.1-µF capacitor placed as close

as possible to the appropriate device terminals.

D The no-connection (NC) terminal on the package should be connected to GND.

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