TLC32040M

ANALOG INTERFACE CIRCUIT

POST OFFICE BOX 655303

4–28

PRINCIPLES OF OPERATION

A/D converter performance specifications

Fundamental performance specifications for the A/D converter circuitry are presented in the A/D converter

operating characteristics section of this data sheet. The design of the A/D converter circuitry with switched-

capacitor techniques provides an inherent sample and hold.

analog output

The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier outputs

are brought out of the integrated circuit. This amplifier can drive transformer hybrids or low-impedance loads

directly in either a differential or single-ended configuration.

D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing

The frequency response of this filter is presented in the following pages. This response results when the

low-pass switched-capacitor filter clock frequency is 288 kHz. Like the A/D filter, the transfer function of this filter

is frequency scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided on the output

of the D/A low-pass filter to greatly attenuate any switched-capacitor clock feedthrough.

The D/A conversion rate is then attained by frequency dividing the 288-kHz switched-capacitor filter clock with

TX Counter B. Thus, unwanted aliasing is prevented because the D/A conversion rate is an integral submultiple

of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.

asynchronous versus synchronous operation

If the transmit section of the AIC (low-pass filter and DAC) and receive section (band-pass filter and ADC) are

operated asynchronously, the low-pass and band-pass filter clocks are independently generated from the

master clock signal. Also, the D/A and A/D conversion rates are independently determined. If the transmit and

receive sections are operated synchronously, the low-pass filter clock drives both low-pass and band-pass

filters. In synchronous operation, the A/D conversion timing is derived from, and is equal to, the D/A conversion

timing. (See description of WORD/BYTE in the Terminal Functions table.)

D/A converter performance specifications

Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter

operating characteristics section of the data sheet. The D/A converter has a sample and hold that is realized

with a switched-capacitor ladder.

system frequency response correction

(Sin x)/x correction circuitry is performed in digital signal processor software. The system frequency response

can be corrected via DSP software to 0.1-dB accuracy to a band-edge of 3000 Hz for all sampling rates. This

correction is accomplished with a first-order digital correction filter, which requires only seven SMJ320

instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of only 1.1%

and 1.3% for sampling rates of 8 and 9.6 kHz, respectively [see the (sin x)/x correction section for more details].