1–2

1.3

Terminal Assignments

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

INLP

INLM

REFI

AnaPD

HPByp

MODE2

OSFL

DigPD

TEST

CMODE

MODE0

LRClk

INRP

INRM

REFO

LGND

Vlogic

NC

MODE1

OSFR

MCLK

Fsync

DOUT

SCLK

DW PACKAGE

(TOP VIEW)

NC – No internal connection

1.4

Ordering Information

PACKAGE

TA

SMALL OUTLINE

(DW)

0

°C to 70°C

TLC320AD57CDW

1.5

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AnaPD

6

I

Analog power-down mode. The analog power-down mode disables the analog

modulators. The single-bit modulator outputs become invalid, which renders the

outputs of the digital filters invalid. When AnaPD is pulled low, normal operation of the

device resumes.

AVDD

4

I

Analog supply voltage

AVSS

5

I

Analog ground

CMODE

12

I

Clock mode. CMODE selects between two methods of determining the master clock

frequency. When CMODE is high, the master clock input is 384

× the conversion

frequency. When CMODE is low, the master clock input is 256

× the conversion

frequency.

DOUT

16

O

Data output. DOUT transmits the sigma-delta audio analog-to-digital converter (ADC)

output data to a digital signal processor (DSP) serial port or other compatible serial

interface and is synchronized to SCLK. DOUT is low when DigPD is high.

DVDD

18

I

Digital supply voltage