2–5

available as a master are 16-bit modes. Two of the modes differ as MSB first versus LSB first. These two

modes set SCLK = LRClk

× 32. This is one half the frequency used in the other transfer modes [see Figures

2–3(d) and 2–3(e)]. The third 16-bit mode provides the data MSB first with one clock delay after LRClk [see

Figure 2–3(a)].

15

14

. . .

1

0

15

14

. . .

10

(a) MASTER MODE (Fsync bound)

17

16

. . .

1

0

17

16

. . .

10

17

64 SCLKs

(b) 18-BIT MASTER MODE

64 SCLKs

01

. . .

16

17

0

1

. . .

16

17

(c) 18-BIT MASTER MODE

14

. . .

10

15

14

. . .

10

15

32 SCLKs

Right

Left

(d) DSP CONTINUOUS MODE

32 SCLKs

1

. . .

14

15

01

. . .

14

15

0

(e) DSP CONTINUOUS MODE

Mode 011

SCLK

Fsync

DOUT

LRClk

Mode 100

SCLK

Fsync

DOUT

LRClk

Mode 101

SCLK

Fsync

DOUT

LRClk

Mode 110

SCLK

Fsync

DOUT

LRClk

Mode 111

SCLK

Fsync

DOUT

LRClk

15

0

Left

Left

Left

Left

Right

Right

Right

Right

64 SCLKs

Figure 2–3. Serial Master Transfer Modes