TLK2500IRCP

1.6 Gbps to 2.5 Gbps TRANSCEIVER

SLLS356B – JUNE 1999 – REVISED JANUARY 2000

6

POST OFFICE BOX 655303

receive interface (continued)

Rx Byte A

Rx Byte B

Rx Byte A

DINRXP,

DINRXN

RXD[1–15]

RX_CLK

Tlatency†

Rx Byte B

. . .

† This figure for illustration only. Tlatency is larger than shown.

Figure 4. Receiver Latency

serial to parallel

Serial data is received on the DINRXP, DINRXN pins. The interpolator and clock recovery circuit will lock to the

data stream if the clock to be recovered is within

±200 PPM of the internally generated bit rate clock. The

recovered clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel

shift registers. The 10 bit wide parallel data is then multiplexed and fed into two separate 8B/10B decoders

where the data is then synchronized to the incoming data steam word boundary by detection of the K28.5

synchronization pattern.

comma detect and 8b/10b decoding

The 8B/10B decoder converts 10 bit encoded data back into 8 bits. The comma detect circuit is designed to

provide for byte synchronization to an 8b/10b transmission code. When parallel data is clocked into a parallel

to serial converter, the byte boundary that was associated with the parallel data is now lost in the serialization

of the data. When the serial data is received and converted to parallel format again a way is needed to be able

to recognize the byte boundary again. Generally this is accomplished through the use of a synchronization

pattern. This is generally a unique a pattern of 1’s and 0’s that either cannot occur as part of valid data or it is

a pattern that repeats at defined intervals. 8b/10b encoding contains a character called the comma (b’0011111’

or b’1100000’) which is used by the comma detect circuit to align the received serial data back to its original byte

boundary. The decoder detects the K28.5 comma, generating a synchronization signal aligning the data to their

10 bit boundaries for decoding. It then converts the data back into 8 bit data, removing the control words. The

output from the two decoders are latched into the 16 bit register synchronized to the recovered parallel data

clock (RX_CLK) and valid on the rising edge of RX_CLK.

The decoding generates the data bits RXD[0:15] and two additional status signals, RX_DV and RX_ER. When

RX_DV is asserted and RX_ER is deasserted, a valid data word has been received and output on the RXDx

pins. When RX_DV is deasserted and RX_ER is asserted, a carrier extend was received and the data bits are

set to F7F7h. If RX_DV and RX_ER are both asserted, the decoder has either received an error propagation

code (K30.7) or an invalid code. In the former case, the data bits are set to FEFEh. The data bits are set to 0000h

if the received code was invalid. When RX_DV and RX_ER are both deasserted, an IDLE was received and

the data bits are set to either BCC5h or BC50h.

Table 2. Receive Data Controls

RECEIVED ENCODED 10-BIT INPUT

RX_DV

RX_ER

IDLE (<K28.5, D5.6>,<K28.5, D16.2>)

0

0

Carrier extend (K23.7)

0

1

Normal data character

1

0

Receive error propagation (K30.7)

1

1