TLK2500IRCP

1.6 Gbps to 2.5 Gbps TRANSCEIVER

SLLS356B – JUNE 1999 – REVISED JANUARY 2000

3

POST OFFICE BOX 655303

transmit interface

The transmitter portion registers incoming 16-bit wide data (TXD[0:15]) on the rising edge of GTX_CLK. The

data is then 8B/10B encoded, serialized and transmitted sequentially over the differential high speed I/O

channel. The clock multiplier, multiplies the reference clock (GTX_CLK) by a factor of 10 times, providing a

signal which is fed to the parallel-to-serial shift register. Data is transmitted LSB (D0) first. The transmitter also

outputs commas when the link is idle for byte synchronization. The transmitter depends on the receive side

being active to achieve link synchronization. This provides automatic sync and resync during normal operation,

as needed. The LCKREFN pin can be used to override this feature.

low-speed data bus

The transmit bus interface accepts 16 bit wide single-ended TTL parallel data at the TXD[0–15] pins. Data is

valid on the rising edge of GTX_CLK when TX_EN is asserted high. The GTX_CLK is used as the byte clock.

The data, enable and clock signals must be properly aligned as shown in Figure 1. Detailed timing information

can be found in the TTL input switching characteristics table.

GTX_CLK

TX_EN, TX_ER

TXDn

tSETUP

tHOLD

Figure 1. Transmit Timing Waveform

transmission latency

The data transmission latency of the TLK2500 is defined as the delay from the initial 16-bit word load to the serial

transmission of bit 0. The minimum latency is 34 bit times; the maximum is 38 bit times.

Tx Word A

Tx Word B

T latency

DOUTTXP,

DOUTTXN

TXD[0–15]

GTX_CLK

Tx Word C

Tx Word B

† This figure for illustration only. Tlatency is larger than shown.

Figure 2. Transmitter Latency