TLV1504, TLV1508

2.7 V TO 5.5 V, 10-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN

SLAS251 – DECEMBER 1999

23

POST OFFICE BOX 655303

5.5 V, SCLK frequency = 20 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

Integral linearity error (INL) (see Note 4)

±0.5

LSB

Differential linearity error (DNL)

See Note 3

±0.5

LSB

EO

Offset error (see Note 5)

See Note 3

±1

LSB

EG

Gain error (see Note 5)

See Note 3

±0.5

±1.2

LSB

ET

Total unadjusted error (see Note 6)

±1

LSB

SDI = B000h

200h

(512D)

Self-test output code (see Table 1 and Note 7)

SDI = C000h

000h

(0D)

SDI = D000h

3FFh

(1023D)

Internal OSC

OSC = 4 MHz to 6 MHz

2.17

2.6

3.6

µs

tconv

Conversion time

External SCLK

(13XDIV)

fSCLK

tsample Sampling time

At 1 k

Ω

600

ns

tt(I/O)

Transition time for EOC, INT

50

ns

tt(CLK)

Transition time for SDI, SDO

25

ns

† All typical values are at TA = 25°C.

NOTES:

3. Analog input voltages greater than that applied to REFP convert as all ones (1111111111), while input voltages less than that applied

to REFM convert as all zeros (00000000). The device is functional with reference down to 2 V (VREFP – VREFM); however, the

electrical specifications are no longer applicable.

4. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.

5. Zero error is the difference between 0000000000 and the converted output for zero input voltage: full-scale error is the difference

between 1111111111 and the converted output for full-scale input voltage.

6. Total unadjusted error comprises linearity, zero, and full-scale errors.

7. Both the input data and the output codes are expressed in positive logic.