TLV320AD11A

3.3 V INTEGRATED ADSL OVER POTS CODEC

SLWS087B – JUNE 1999 – REVISED MARCH 2000

16

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

register programming (continued)

SCR13 – EC channel digital gain control register

Address:1101b

Contents at reset: 00000000b

SCR13 has the same format as SCR11. Check with SCR11 for details.

SCR14 – Miscellaneous control register 2

Address:1110b

Contents at reset: 00000000b

D7

D6

D5

D4

D3

D2

D1

D0

REGISTER

VALUE (HEX)

DESCRIPTION

0

0

0

0

–

–

–

1

One write operation reset. (see Note 9)

0

0

0

0

–

–

1

–

Enable FIFO

0

0

0

0

–

1

–

–

Bypass EC DHPF (25.875 kHz)

0

0

0

0

1

–

–

–

ECP and ECM are connected to weakly driven mid-supply. It can only be

used during EC power-down mode.

NOTE 9: Write-synchronized operation: A 1 is written to bit D0 of SCR14 register after pin ONE_WE is set to high. This sets the start point for

the TX/EC operation. During the first WETX pulse, data is written to the TX channel. During the second WETX pulse, data is written

to the EC channel. D0 of SCR14 is always self-cleared; therefore, the read-back value of bit D0 of SCR14 is always zero.

device initialization time

The TLV320AD11A completes all calibration and initialization in less than 1 second. This includes reference

settling time (

≈950 µs), one rest after power up (1 serial frame), VCXODAC configuration (2 serial frames),

TX/RX gain select (4 serial frames), and self-calibration of the DAC (256X113 ns). Each 16-bit frame requires

up to 5

µs. The host processor needs to initiate this process upon a successful power up.

power-down

Both hardware and software power-down modes are provided. The serial interface is operative when the codec

is in power-down mode. By sending commands through serial interface, either the codec or part of the codec,

can be software powered down. All the references are kept on in the software power-down mode. The codec

can also be hardware powered down by setting PWDN pin to high. All the references are shut off in the hardware

power-down mode. The contents of the registers will not change in either power-down modes.

power supply grouping recommendation

The following power supply grouping is recommended for best performance of this device. Ferrite beads are

used to separate group1, group 2, and group 3 if the same 3.3-V analog power source is shared