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TLV320AD11APZ Datasheet(PDF) 20 Page - Texas Instruments

Part # TLV320AD11APZ
Description  3.3 V INTEGRATED ADSL OVER POTS CODEC
PDF  28 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TLV320AD11APZ Datasheet(HTML) 20 Page - Texas Instruments

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TLV320AD11A
3.3 V INTEGRATED ADSL OVER POTS CODEC
SLWS087B – JUNE 1999 – REVISED MARCH 2000
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
parallel port (see Figures 2, 3, and 4)
PARAMETER
MIN
TYP
MAX
UNIT
tc1
Period, CLKIN
28.3
ns
t 2
Cycle time INT
OSEN=0
16
tc2
Cycle time, INT
OSEN=1
8
CLKIN
tc3
Period, CLKOUT
8
td1
Delay time, keep-out zone end to INT
↑
5
ns
td2
Delay time, keep-out zone end (CLKIN
↑)to OE↓/CS↓
0
ns
td3
Delay time, keep-out zone end to WETX
↓/CS↓ or WEEC↓/CS↓
0
ns
td4
Delay time, data valid after OE
↓/CS↓
15
ns
td5
Delay time, data becomes Hi-Z after OE
↑/CS↑
5
ns
td6
Delay time, keep-out zone end to SCLK/READY
↑
14.2
ns
td7
Delay time, SCLK/READY
↓ to keep-out zone
14.2
ns
td9
Delay time, time between the rising edge of WETX/WEEC to the rising edge of CS
5
ns
th1
Hold time, data valid after WETX
↑
5
ns
th2
Hold time, data valid after WEEC
↑
5
ns
th3
Hold time, SYNC keep high after CLKIN
↑
5
ns
tsu1
Setup time, data valid before WETX
↑
15
ns
tsu2
Setup time, data valid before WEEC
↑ or second WETX↑
15
ns
tsu3
Setup time, SYNC is high before CLKIN
↑
10
ns
tw1
Pulse width, keep-out zone time
1
CLKIN
tw2
Pulse width, OE
20
ns
tw3
Pulse width, WETX or WETX first pulse
28
ns
tw4
Pulse width, WEEC or WETX second pulse
28
ns
tw5
Pulse width, SYNC
28
ns
serial port (see Figure 6)
PARAMETER
MIN
TYP
MAX
UNIT
tc4
Cycle time, SCLK
8
CLKIN
td8
Delay time, SCLK rising edge to SDO valid
15
ns
th4
Hold time, FS keep high after SCLK
↓
5
ns
th5
SDI valid after SCLK
↓
5
ns
tsu4
Setup time, FS valid before SCLK
↓
20
ns
tsu5
SDI valid before SCLK
↓
20
ns
tw6
FS pulse width
28
ns



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