TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998

20

POST OFFICE BOX 655303

APPLICATION INFORMATION

hardware interfacing

input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD

line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the

DAC latch update (LDAC), chip select (CS) and frame sync (FS) signals for the TLV5604. The active low power

down pin (PD) of the TLV5604 is pulled high to ensure that the DACs are enabled.

RxD

TxD

P3.3

P3.4

MCS

SDIN

SCLK

FS

CS

LDAC

REF

VDD

PD

VOUTA

VOUTB

VOUTC

VOUTD

VSS

TLV5604

P3.4

REFINAB

REFINCD

Figure 18. TLV5604 Interfaced with MCS®51

software

The example is the same as for the TMS320C203 in this datasheet, but adapted for a MCS

®51 controller. It

generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and it’s quadrature

(cosine) signal as the differential signal between VOUTC and VOUTD.

The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses

LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The

samples are stored as a look-up table, which describes one full period of a sine wave.

The serial port of the controller is used in Mode 0, which transmits 8 bits of data on RxD, accompanied by a

synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the

TLV5604. The CS and FS signals are provided in the required fashion through control of IO port 3, which has

bit addressable outputs.

MCS is a registered trademark of Intel Corporation.