software START conversion (continued)

internal clock

With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. Conversion begins 6 clocks after sampling

begins. The internal clock begins at the rising edge of WR. The internal clock is disabled after each conversion. Subsequent sampling begins

at the rising edge of RD.

OR

Auto Powerdown

ADC

CS

WR

RD

INTCLK

D[0:7]

INT

EOC

Config

Data

ADC

Data

tsu(CSL_WRL)

t

h(WRH_CSH)

t(sample)

tsu(DAV_WRH)

t

h(WRH_DAV)

tc

t su(CSL_RDL)

th(RDH_CSH)

ten(RDL_DAV)

t

dis(RDH_DAV)

tc

t

(STARTOSC)

t(STARTOSC)

t(sample)

45

6

0

4

5

015

15

Auto Powerdown

Figure 7. Input Conversion – Software Start, Internal Clock