TLV571DW datasheet(15/27 Pages) TI

15 / 27 page

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

simplified analog input analysis

Using the equivalent circuit in Figure 10, the time required to charge the analog input capacitance from 0 to VS

within 1/2 LSB, tch(1/2 LSB), can be derived as follows.

The capacitance charging voltage is given by:

Where

Rt = Rs + Ri

Ri = Ri(ADC)

tch = Charge time

C(t) +

1–e

–t

RtCi

The input impedance Ri is 718 Ω at 5 V, and is higher (~ 1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given

by:

VC (1/2 LSB) = VS – (VS/512)

Equating equation 1 to equation 2 and solving for cycle time tc gives:

and time to change to 1/2 LSB (minimum sampling time) is:

tch (1/2 LSB) = Rt × Ci × ln(512)

S *

512

+ V

1–e

–t

RtCi

Where

ln(512) = 6.238

Therefore, with the values given, the time for the analog input signal to settle is:

tch (1/2 LSB) = (Rs + 718 Ω) × 15 pF × ln(512)

This time must be less than the converter sample time shown in the timing diagrams. Which is 6x SCLK.

tch (1/2 LSB) ≤ 6x 1/f(SCLK)

Therefore the maximum SCLK frequency is:

Max(f(SCLK)) = 6/tch (1/2 LSB) = 6/(ln(512) × Rt × Ci)

(1)

(2)

(3)

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(5)

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