TMS320VC33 datasheet(48/57 Pages) TI

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TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

HOLD timing (continued)

HOLD

HOLDA

STRB, PAGEx

R/W

A[23:0]

D[31:0]

Write Data

tsu(HOLD−H1L)

tv(H1L−HOLDA)

tsu(HOLD−H1L)

tw(HOLD)

tw(HOLDA)

tv(H1L-HOLDA)

td(H1L-SH)H

tdis(H1L-S)

ten(H1L-S)

ten(H1L-RW)

tdis(H1L-RW)

tdis(H1L-A)

ten(H1L-A)

tdis(H1H-D)

NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle

after HOLD goes back high.

Figure 33. Timing for HOLD/HOLDA (After Write)

HOLD

HOLDA

STRB, PAGEx

R/W

A[23:0]

D[31:0]

Read Data

tsu(HOLD−H1L)

tv(H1L−HOLDA)

tsu(HOLD−H1L)

tw(HOLD)

tw(HOLDA)

td(H1L-SH)H

tdis(H1L-S)

ten(H1L-S)

ten(H1L-RW)

tdis(H1L-RW)

tdis(H1L-A)

ten(H1L-A)

tv(H1L−HOLDA)

NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle

after HOLD goes back high.

Figure 34. Timing for HOLD/HOLDA (After Read)

TMS320VC33 Datasheet(PDF) 48 Page - Texas Instruments

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