TMS370 datasheet(14/49 Pages) TI

14 / 49 page

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

privileged operation and EEPROM WPO (continued)

nonprivileged mode, thus disabling write operations to specific configuration control bits within the peripheral

file. Table 8 lists the system configuration bits which are write-protected during the nonprivileged mode and must

be configured by software prior to exiting the privileged mode.

Table 8. Privileged Bits

CONTROL BIT

NAME

LOCATION

CONTROL BIT

SCCR0

P010.5

P010.6

PF AUTO WAIT

OSC POWER

SCCR1

P011.2

P011.4

MEMORY DISABLE

AUTOWAIT DISABLE

SCCR2

P012.0

P012.1

P012.3

P012.4

P012.6

P012.7

PRIVILEGE DISABLE

INT1 NMI

CPU STEST

BUS STEST

PWRDWN / IDLE

HALT / STANDBY

SCIPRI

P05F.4

P05F.5

P05F.6

P05F.7

SCI ESPEN

SCIRX PRIORITY

SCITX PRIORITY

SCI STEST

T1PRI

P04F.6

P04F.7

T1 PRIORITY

T1 STEST

† The privileged bits are shown in a bold typeface in Table 10.

The write protect override (WPO) mode is an external hardware method of overriding the write protection

registers (WPR) of data EEPROM on the TMS370Cx0x. WPO mode is entered by applying a 12-V input to the

MC pin after the RESET pin input goes high (logic 1). The high voltage (+ 12 V) on the MC pin during the WPO

mode is not the programming voltage for the data EEPROM or program EPROM. All EEPROM programming

voltages are generated on-chip. The WPO mode provides hardware system level capability to modify the

content of data EEPROM while the device remains in the application but only while requiring a 12-V external

input on the MC pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx0x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For

mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the

time the mask is manufactured.

The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping

the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes

is entered by executing the IDLE instruction when the PWRDWN / IDLE bit in SCCR2 has been set to 1. The

HALT / STANDBY bit in SCCR2 controls the low-power mode selection.

In the STANDBY mode (HALT / STANDBY = 0), all CPU activity and most peripheral module activity stops;

however, the oscillator, internal clocks, timer 1 and the receive-start bit detection circuit of the serial

communications interface remain active. System processing is suspended until a qualified interrupt (hardware

RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the SCI1) is

detected.

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