TMS370 datasheet(4/49 Pages) TI

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

description (continued)

Table 1. Memory Configurations

DEVICE

PROGRAM MEMORY

(BYTES)

DATA MEMORY

(BYTES)

28-PIN PACKAGE

ROM

EPROM

RAM

EEPROM

TMS370C002A

—

256

FN – PLCC

TMS370C302A

—

256

—

FN – PLCC

TMS370C702

—

256

FN – PLCC

SE370C702†

—

256

FZ – CLCC

† System evaluators and development are for use only in prototype environment and their reliability has not been characterized.

The suffix letter (A) appended to the device name (shown in the first column of Table 1) indicates the

configuration of the device. ROM and EPROM devices have different configurations as indicated in Table 2.

ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 2. Suffix Letter Configuration

DEVICE

WATCHDOG TIMER

CLOCK

LOW-POWER MODE

EPROM without A

Standard

Divide-by-4 (standard oscillator)

Enabled

Standard

Di id b 4

ROM A

Hard

Divide-by-4 or

Divide-by-1 (PLL)

Enabled or disabled

Simple

Divide-by-1 (PLL)

The 8K bytes of mask-programmable ROM in the associated TMS370Cx0x devices are replaced in the

TMS370C702 with 8K bytes of EPROM. All other available memory and on-chip peripherals are identical, with

the exception of no data EEPROM on the TMS370C302 devices. The one-time programmable (OTP)

(TMS370C702) device and reprogrammable device (SE370C702) are available.

TMS370C702 OTP devices are available in plastic packages. This microcontroller is effective to use for

immediate production updates for other members of the TMS370Cx0x family or for low-volume production runs

when the mask charge or cycle time for low-cost mask ROM devices is not practical.

The SE370C702 has a windowed ceramic package to allow reprogramming of the program EPROM memory

during the development-prototyping phase of design. The SE370C702 devices allow quick updates to

breadboards and prototype systems while iterating initial designs.

The TMS370Cx0x family provides two low-power modes (STANDBY and HALT) for applications where

low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In

the STANDBY mode, the internal oscillator and the general purpose timer remain active. In the HALT mode,

all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both

low-power modes.

The TMS370Cx0x features advanced register-to-register architecture that allows direct arithmetic and logical

operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to

the contents of register 47 and store the result in register 47). The TMS370Cx0x family is fully

instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller

family.

The TMS370Cx0x devices have two operational modes of serial communications provided by the SCI1 module.

The SCI1 allows standard RS-232-C communications with other common data transmission equipment.

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