TPIC43T01, TPIC43T02

THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS

SLIS098 – APRIL 2000

13

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

VDD

UVLO

3 Counts

PUC

S/S

Internal

5.8 MHz

OSC

÷ 32

Charge Pump

UV

t(DG)

PWM

(22 KHz)

CPUV

D

Q

Q

CLR

ENA

Shutdown

Latch

VDD

OSC

Lock

OSC

Lock

Detect

Lock

Counter

LTCLR

ILIM

OCSD

OCSD

LT

ENA

ENA

CLR

t(DG)

Figure 6. Shutdown Logic Block Diagram

FG amplifier

The FG amplifier amplifies the ac signal from the FG variable-reluctance pickup and converts it to a digital signal

for internal use in the FG frequency control loop (see Figure 7). Figure 8 illustrates the generation of the

FGSOUT signal in the FG amplifier section. Two comparators driving an RS latch are used with the upper

comparator threshold is connected to the FG bias voltage. This provides controlled hysteresis above the FGIN+

amplifier input reference voltage and zero-crossing detection at the input reference voltage.

_

+

_

+

R

S

Q

FG

Comparator

_

+

FGS Buffer

FG Amp

_

+

1/2 VDD

+ 180 mV

1/2 VDD

Band-Gap

Buffer

OP-Amp

FGSOUT

FGOUT

FGIN–

FGIN+

330 k

Ω

1 k

Ω

1

µF

FG

Winding

150 pF

Figure 7. FG Signal Conditioning Schematic