TPIC43T01, TPIC43T02

THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS

SLIS098 – APRIL 2000

21

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

current limit/over-current shutdown (continued)

The deglitch timer prevents the ILIM COMP high from being recognized unless it occurs for the duration of the

timer, after which a high IDET level occurs. This IDET level is used to terminate, or latch off the upper gate drive

being driven by PWM for the remainder of the PWM interval. This ILIM latch and deglitch timer clears at the start

of each new PWM cycle; thus, a cycle-by-cycle PWM controlled current limit is implemented.

Current spike from trr

t(DG) = 0.5 to 6.5 µs

t(DE-GLITCH)

Amplitude

VOCSD

VL

VCC – VSENSE

time

ILIM

COMP

IDET

OCSD

COMP

OCSD

Figure 16. Normal Motor Current Waveform With trr Spike at Start of PWM Cycle

Amplitude

High Ipeak from shorted phase winding

or shorted-phase-to-GND(> 5 A depending on the value of R(SENSE))

VOCSD

VL

VCC – VSENSE

t(ocsd) = 0.5 to 2.5 µs

Combination of IDET high and OCSDCOMP high

sets OSCD latch

Latches high until S/S cycles

time

Figure 17. Motor Current Waveform With Shorted Phase Winding or Shorted Phase to GND