TPS2202, TPS2202Y

DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES

FOR SERIAL PCMCIA CONTROLLERS

SLVS103A – DECEMBER 1994 – REVISED AUGUST 1995

6–5

POST OFFICE BOX 655303

dc characteristics

PARAMETER

TEST CONDITIONS

TPS2202

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

†

5 V to xVCC

160

m

Ω

†

3 V to xVCC

225

m

Ω

Switch resistances†

5 V to xVPP

6

3 V to xVPP

6

Ω

12 V to xVPP

1

Clamp low voltage

Ipp at 10 mA

0.8

V

Clamp low voltage

ICC at 10 mA

0.8

V

I

High impedance state

TA = 25°C

1

10

Leakage current

Ipp High-impedance state

TA = 85°C

50

µA

Leakage current

ICC High impedance state

TA = 25°C

1

10

µA

ICC High-impedance state

TA = 85°C

50

Input current

IDD

VO(AVCC) = VO(BVCC) = 5 V,

VO(AVPP) = VO(BVPP) = 12 V

83

150

µA

Input current

IDD in shutdown

VO(BVCC) = VO(AVCC) = VO(AVPP)

= VO(BVPP) = high Z

1

µA

Power-ready threshold, PWR_GOOD

10.72

11.05

11.4

V

Power-ready hysteresis, PWR_GOOD (12-V mode)

50

mV

Short circuit output current limit

IO(xVCC)

TJ = 85°C,

0.75

1.3

1.9

A

Short-circuit output-current limit

IO(xVPP)

J

,

Output powered up into a short to GND

120

200

400

mA

† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

PARAMETER

TEST CONDITIONS

TPS2202

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t

Output rise time

VO(xVCC)

1.2

ms

tr

Output rise time

VO(xVPP)

5

ms

tf

Output fall time

VO(xVCC)

10

ms

tf

Output fall time

VO(xVPP)

14

ms

§

LATCH

↑ to VO(

)

ton

5.8

ms

§

LATCH

↑ to VO(xVPP)

toff

18

ms

t d

Propagation delay (see Figure 1§)

LATCH

↑ to xVCC (3 V)

ton

5.8

ms

tpd

Propagation delay (see Figure 1§)

LATCH

↑ to xVCC (3 V)

toff

28

ms

LATCH

↑ to xVCC (5 V)

ton

4

ms

LATCH

↑ to xVCC (5 V)

toff

30

ms

‡ Refer to Parameter Measurement Information

§ Propagation delays are with CL = 100 µF.