TPS70145, TPS70148, TPS70151, TPS70158, TPS70102

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS

WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS

SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

2

POST OFFICE BOX 655303

description (continued)

The TPS701xx family of voltage regulators offers very low dropout voltage and dual outputs with power up

sequence control, which is designed primarily for DSP applications. These devices have extremely low noise

output performance without using any added filter bypass capacitors and are designed to have a fast transient

response and be stable with 10 uF low ESR capacitors.

These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable/adjustable voltage

options. The 3.3-V output regulator (regulator 1) can support up to 500 mA, and the other regulator (regulator

2) can support up to 250 mA. Separate voltage inputs allow the designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV

on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is

a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of

225

µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal

to EN (enable) shuts down both regulators, reducing the input current to 1

The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two

the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high

be turned on first. The SEQ pin is connected to an internal pullup current source.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator

is turned off(disabled).

The PG1 pin reports the voltage conditions at the VOUT1, which can be used to implement a SVS (power on

reset) for the circuitry supplied by regulator 1.

The TPS701xx features a RESET (SVS, POR, or Power On Reset). RESET output initiates a reset in DSP

logic high state, RESET will go to a high impedance state after 120 ms delay. RESET will go to logic low state

The device has an undervoltage lockout UVLO circuit which prevents the internal regulators from turning on until

VIN1 reaches 2.5V.

AVAILABLE OPTIONS

TJ

REGULATOR 1

VO (V)

REGULATOR 2

VO (V)

TSSOP

(PWP)

3.3 V

1.2 V

TPS70145PWP

3.3 V

1.5 V

TPS70148PWP

–40

°Cto125°C

3.3 V

1.8 V

TPS70151PWP

– 40

°C to 125°C

3.3 V

2.5 V

TPS70158PWP

Adjustable

(1.22 V to 5.5 V)

Adjustable

(1.22 V to 5.5 V)

TPS70102PWP

NOTE: The TPS70102 is programmable using external resistor dividers (see

application information) The PWP package is available taped and reeled. Add

an R suffix to the device type (e.g., TPS70102PWPR).