TPS70102 datasheet(21/34 Pages) TI

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VOUT2

VIN1

VIN2

SEQ

VOUT1

VSENSE1

PG1

MR2

RESET

MR1

VSENSE2

VOUT2

TPS701xxPWP

(Fixed Output Option)

VIN

VOUT1

MR1

0.1

µF

RESET

µF

0.1

µF

MR2

>2 V

<0.7 V

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS

WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS

SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

sequencing timing diagram

The following figures provide a timing diagram of how this device functions in different configurations.

Application condition; MR2 is tied to PG1, VIN1

and VIN2 are tied to same input voltage, the SEQ

pin is tied to logic low and the device is toggled

with enable (EN) function.

When the device is enabled (EN is pulled low)

VOUT1 will turn on first and VOUT2 will remain off

until VOUT1 reaches to approximately 83% of its

regulated output voltage. At that time VOUT2 will

be turned on. When VOUT1 reaches to 95% of its

regulated output the PG1 will turn on (active high).

Since MR2 is connected to PG1 for this

application, it will follow the logic of PG1. When

VOUT2 reaches to 95% of its regulated voltage,

RESET will switch to high voltage level after

120 ms delay (see Figure 37).

83%

95%

120ms

VOUT2

VOUT1

PG1

MR1

MR2

(MR2 tied to PG1)

RESET

SEQ

95%

83%

Figure 37. Timing When SEQ = Low

TPS70102 Datasheet(PDF) 21 Page - Texas Instruments

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